Figure 12 from Air spacer for 10nm FinFET CMOS and beyond

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Impact of MOL/BEOL Air-Spacer on Parasitic Capacitance and Circuit

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Miniaturization of CMOS. - Abstract - Europe PMC

Scaling aligned carbon nanotube transistors to a sub-10 nm node

IEDM 2022 – TSMC 3nm - SemiWiki

a) 3D view of the bulk FinFET tri-gate structure, b) 3D cross section

Effect of air spacer on analog performance of underlap tri-gate FinFET - ScienceDirect

Figure 2 from An air spacer technology for improving short-channel immunity of MOSFETs with raised source/drain and high-/spl kappa/ gate dielectric

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Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era - ScienceDirect

Next to FinFET, How Will ESD Suffer? - In Compliance Magazine

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Typical STEM of 2a) Front End of Line Air Spacer Formation in 10

Figure 4 from Air spacer for 10nm FinFET CMOS and beyond